Module X86_asm_reg

include module type of X86_asm_reg_types
type r8l = [
  1. | `AL
  2. | `BL
  3. | `CL
  4. | `DL
  5. | `SIL
  6. | `DIL
  7. | `BPL
  8. | `SPL
  9. | `R8B
  10. | `R9B
  11. | `R10B
  12. | `R11B
  13. | `R12B
  14. | `R13B
  15. | `R14B
  16. | `R15B
]

8-bit low byte GPR registers

val __r8l_of_sexp__ : Ppx_sexp_conv_lib.Sexp.t -> r8l
val r8l_of_sexp : Ppx_sexp_conv_lib.Sexp.t -> r8l
val sexp_of_r8l : r8l -> Ppx_sexp_conv_lib.Sexp.t
type r8h = [
  1. | `AH
  2. | `BH
  3. | `CH
  4. | `DH
]

8-bit high-byte GPR registers

val __r8h_of_sexp__ : Ppx_sexp_conv_lib.Sexp.t -> r8h
val r8h_of_sexp : Ppx_sexp_conv_lib.Sexp.t -> r8h
val sexp_of_r8h : r8h -> Ppx_sexp_conv_lib.Sexp.t
type r8 = [
  1. | r8l
  2. | r8h
]

all 8 bit GPR registers

val __r8_of_sexp__ : Ppx_sexp_conv_lib.Sexp.t -> r8
val r8_of_sexp : Ppx_sexp_conv_lib.Sexp.t -> r8
val sexp_of_r8 : r8 -> Ppx_sexp_conv_lib.Sexp.t
type r16 = [
  1. | `AX
  2. | `BX
  3. | `CX
  4. | `DX
  5. | `DI
  6. | `SI
  7. | `BP
  8. | `SP
  9. | `R8W
  10. | `R9W
  11. | `R10W
  12. | `R11W
  13. | `R12W
  14. | `R13W
  15. | `R14W
  16. | `R15W
]

16-bit GPR registers

val __r16_of_sexp__ : Ppx_sexp_conv_lib.Sexp.t -> r16
val r16_of_sexp : Ppx_sexp_conv_lib.Sexp.t -> r16
val sexp_of_r16 : r16 -> Ppx_sexp_conv_lib.Sexp.t
type r32 = [
  1. | `EAX
  2. | `EBX
  3. | `ECX
  4. | `EDX
  5. | `EDI
  6. | `ESI
  7. | `EBP
  8. | `ESP
  9. | `R8D
  10. | `R9D
  11. | `R10D
  12. | `R11D
  13. | `R12D
  14. | `R13D
  15. | `R14D
  16. | `R15D
]

32-bit GPR registers

val __r32_of_sexp__ : Ppx_sexp_conv_lib.Sexp.t -> r32
val r32_of_sexp : Ppx_sexp_conv_lib.Sexp.t -> r32
val sexp_of_r32 : r32 -> Ppx_sexp_conv_lib.Sexp.t
type r64 = [
  1. | `RAX
  2. | `RBX
  3. | `RCX
  4. | `RDX
  5. | `RDI
  6. | `RSI
  7. | `RBP
  8. | `RSP
  9. | `R8
  10. | `R9
  11. | `R10
  12. | `R11
  13. | `R12
  14. | `R13
  15. | `R14
  16. | `R15
]

64-bit GPR registers

val __r64_of_sexp__ : Ppx_sexp_conv_lib.Sexp.t -> r64
val r64_of_sexp : Ppx_sexp_conv_lib.Sexp.t -> r64
val sexp_of_r64 : r64 -> Ppx_sexp_conv_lib.Sexp.t
type r128 = [
  1. | `XMM0
  2. | `XMM1
  3. | `XMM2
  4. | `XMM3
  5. | `XMM4
  6. | `XMM5
  7. | `XMM6
  8. | `XMM7
  9. | `XMM8
  10. | `XMM9
  11. | `XMM10
  12. | `XMM11
  13. | `XMM12
  14. | `XMM13
  15. | `XMM14
  16. | `XMM15
]

SSE register types

val __r128_of_sexp__ : Ppx_sexp_conv_lib.Sexp.t -> r128
val r128_of_sexp : Ppx_sexp_conv_lib.Sexp.t -> r128
val sexp_of_r128 : r128 -> Ppx_sexp_conv_lib.Sexp.t
type r256 = [
  1. | `YMM0
  2. | `YMM1
  3. | `YMM2
  4. | `YMM3
  5. | `YMM4
  6. | `YMM5
  7. | `YMM6
  8. | `YMM7
  9. | `YMM8
  10. | `YMM9
  11. | `YMM10
  12. | `YMM11
  13. | `YMM12
  14. | `YMM13
  15. | `YMM14
  16. | `YMM15
]
val __r256_of_sexp__ : Ppx_sexp_conv_lib.Sexp.t -> r256
val r256_of_sexp : Ppx_sexp_conv_lib.Sexp.t -> r256
val sexp_of_r256 : r256 -> Ppx_sexp_conv_lib.Sexp.t
type ip = [
  1. | `IP
  2. | `EIP
  3. | `RIP
]
val __ip_of_sexp__ : Ppx_sexp_conv_lib.Sexp.t -> ip
val ip_of_sexp : Ppx_sexp_conv_lib.Sexp.t -> ip
val sexp_of_ip : ip -> Ppx_sexp_conv_lib.Sexp.t
type segment = [
  1. | `CS
  2. | `DS
  3. | `ES
  4. | `FS
  5. | `GS
  6. | `SS
]
val __segment_of_sexp__ : Ppx_sexp_conv_lib.Sexp.t -> segment
val segment_of_sexp : Ppx_sexp_conv_lib.Sexp.t -> segment
val sexp_of_segment : segment -> Ppx_sexp_conv_lib.Sexp.t
type segment_base = [
  1. | `FS_BASE
  2. | `GS_BASE
]
val __segment_base_of_sexp__ : Ppx_sexp_conv_lib.Sexp.t -> segment_base
val segment_base_of_sexp : Ppx_sexp_conv_lib.Sexp.t -> segment_base
val sexp_of_segment_base : segment_base -> Ppx_sexp_conv_lib.Sexp.t
type gpr = [
  1. | r8
  2. | r16
  3. | r32
  4. | r64
  5. | r128
  6. | r256
]
val __gpr_of_sexp__ : Ppx_sexp_conv_lib.Sexp.t -> gpr
val gpr_of_sexp : Ppx_sexp_conv_lib.Sexp.t -> gpr
val sexp_of_gpr : gpr -> Ppx_sexp_conv_lib.Sexp.t
type t = [
  1. | gpr
  2. | ip
  3. | segment
  4. | segment_base
]
val __t_of_sexp__ : Ppx_sexp_conv_lib.Sexp.t -> t
val t_of_sexp : Ppx_sexp_conv_lib.Sexp.t -> t
val sexp_of_t : t -> Ppx_sexp_conv_lib.Sexp.t
val width : [ gpr | ip ] -> Bap.Std.size

width reg_type returns the size of the given reg_type

val bitwidth : [ gpr | ip ] -> int

bitwidth reg_type returns the width in bits of the given reg_type

val decode : Bap.Std.reg -> t option

decode reg decodes the given reg provided by the disassembler as an x86 register if that is feasible.