X86_asm_reg (bap-x86-cpu.X86_asm

include module type of X86_asm_reg_types

type r8l = [

| `AL
| `BL
| `CL
| `DL
| `SIL
| `DIL
| `BPL
| `SPL
| `R8B
| `R9B
| `R10B
| `R11B
| `R12B
| `R13B
| `R14B
| `R15B

]

8-bit low byte GPR registers

val __r8l_of_sexp__ : Ppx_sexp_conv_lib.Sexp.t -> r8l

val r8l_of_sexp : Ppx_sexp_conv_lib.Sexp.t -> r8l

val sexp_of_r8l : r8l -> Ppx_sexp_conv_lib.Sexp.t

type r8h = [

| `AH
| `BH
| `CH
| `DH

]

8-bit high-byte GPR registers

val __r8h_of_sexp__ : Ppx_sexp_conv_lib.Sexp.t -> r8h

val r8h_of_sexp : Ppx_sexp_conv_lib.Sexp.t -> r8h

val sexp_of_r8h : r8h -> Ppx_sexp_conv_lib.Sexp.t

type r8 = [

| r8l
| r8h

]

all 8 bit GPR registers

val __r8_of_sexp__ : Ppx_sexp_conv_lib.Sexp.t -> r8

val r8_of_sexp : Ppx_sexp_conv_lib.Sexp.t -> r8

val sexp_of_r8 : r8 -> Ppx_sexp_conv_lib.Sexp.t

type r16 = [

| `AX
| `BX
| `CX
| `DX
| `DI
| `SI
| `BP
| `SP
| `R8W
| `R9W
| `R10W
| `R11W
| `R12W
| `R13W
| `R14W
| `R15W

]

16-bit GPR registers

val __r16_of_sexp__ : Ppx_sexp_conv_lib.Sexp.t -> r16

val r16_of_sexp : Ppx_sexp_conv_lib.Sexp.t -> r16

val sexp_of_r16 : r16 -> Ppx_sexp_conv_lib.Sexp.t

type r32 = [

| `EAX
| `EBX
| `ECX
| `EDX
| `EDI
| `ESI
| `EBP
| `ESP
| `R8D
| `R9D
| `R10D
| `R11D
| `R12D
| `R13D
| `R14D
| `R15D

]

32-bit GPR registers

val __r32_of_sexp__ : Ppx_sexp_conv_lib.Sexp.t -> r32

val r32_of_sexp : Ppx_sexp_conv_lib.Sexp.t -> r32

val sexp_of_r32 : r32 -> Ppx_sexp_conv_lib.Sexp.t

type r64 = [

| `RAX
| `RBX
| `RCX
| `RDX
| `RDI
| `RSI
| `RBP
| `RSP
| `R8
| `R9
| `R10
| `R11
| `R12
| `R13
| `R14
| `R15

]

64-bit GPR registers

val __r64_of_sexp__ : Ppx_sexp_conv_lib.Sexp.t -> r64

val r64_of_sexp : Ppx_sexp_conv_lib.Sexp.t -> r64

val sexp_of_r64 : r64 -> Ppx_sexp_conv_lib.Sexp.t

type r128 = [

| `XMM0
| `XMM1
| `XMM2
| `XMM3
| `XMM4
| `XMM5
| `XMM6
| `XMM7
| `XMM8
| `XMM9
| `XMM10
| `XMM11
| `XMM12
| `XMM13
| `XMM14
| `XMM15

]

SSE register types

val __r128_of_sexp__ : Ppx_sexp_conv_lib.Sexp.t -> r128

val r128_of_sexp : Ppx_sexp_conv_lib.Sexp.t -> r128

val sexp_of_r128 : r128 -> Ppx_sexp_conv_lib.Sexp.t

type r256 = [

| `YMM0
| `YMM1
| `YMM2
| `YMM3
| `YMM4
| `YMM5
| `YMM6
| `YMM7
| `YMM8
| `YMM9
| `YMM10
| `YMM11
| `YMM12
| `YMM13
| `YMM14
| `YMM15

]

val __r256_of_sexp__ : Ppx_sexp_conv_lib.Sexp.t -> r256

val r256_of_sexp : Ppx_sexp_conv_lib.Sexp.t -> r256

val sexp_of_r256 : r256 -> Ppx_sexp_conv_lib.Sexp.t

type ip = [

| `IP
| `EIP
| `RIP

]

val __ip_of_sexp__ : Ppx_sexp_conv_lib.Sexp.t -> ip

val ip_of_sexp : Ppx_sexp_conv_lib.Sexp.t -> ip

val sexp_of_ip : ip -> Ppx_sexp_conv_lib.Sexp.t

type segment = [

| `CS
| `DS
| `ES
| `FS
| `GS
| `SS

]

val __segment_of_sexp__ : Ppx_sexp_conv_lib.Sexp.t -> segment

val segment_of_sexp : Ppx_sexp_conv_lib.Sexp.t -> segment

val sexp_of_segment : segment -> Ppx_sexp_conv_lib.Sexp.t

type segment_base = [

| `FS_BASE
| `GS_BASE

]

val __segment_base_of_sexp__ : Ppx_sexp_conv_lib.Sexp.t -> segment_base

val segment_base_of_sexp : Ppx_sexp_conv_lib.Sexp.t -> segment_base

val sexp_of_segment_base : segment_base -> Ppx_sexp_conv_lib.Sexp.t

type gpr = [

| r8
| r16
| r32
| r64
| r128
| r256

]

val __gpr_of_sexp__ : Ppx_sexp_conv_lib.Sexp.t -> gpr

val gpr_of_sexp : Ppx_sexp_conv_lib.Sexp.t -> gpr

val sexp_of_gpr : gpr -> Ppx_sexp_conv_lib.Sexp.t

type t = [

| gpr
| ip
| segment
| segment_base

]

val __t_of_sexp__ : Ppx_sexp_conv_lib.Sexp.t -> t

val t_of_sexp : Ppx_sexp_conv_lib.Sexp.t -> t

val sexp_of_t : t -> Ppx_sexp_conv_lib.Sexp.t

val width : [ gpr | ip ] -> Bap.Std.size

width reg_type returns the size of the given reg_type

val bitwidth : [ gpr | ip ] -> int

bitwidth reg_type returns the width in bits of the given reg_type

val decode : Bap.Std.reg -> t option

decode reg decodes the given reg provided by the disassembler as an x86 register if that is feasible.