Module ARM

include module type of struct include Arm_types end
module Basic = Arm_types.Basic
exception Lifting_failed of string
type cond = [
  1. | `EQ
  2. | `NE
  3. | `CS
  4. | `CC
  5. | `MI
  6. | `PL
  7. | `VS
  8. | `VC
  9. | `HI
  10. | `LS
  11. | `GE
  12. | `LT
  13. | `GT
  14. | `LE
  15. | `AL
]
val bin_shape_cond : Core_kernel.Bin_prot.Shape.t
val bin_size_cond : 'a -> int
val bin_write_cond : Bin_prot.Common.buf -> pos:Bin_prot.Common.pos -> [< `AL | `CC | `CS | `EQ | `GE | `GT | `HI | `LE | `LS | `LT | `MI | `NE | `PL | `VC | `VS ] -> Bin_prot.Common.pos
val bin_writer_cond : [< `AL | `CC | `CS | `EQ | `GE | `GT | `HI | `LE | `LS | `LT | `MI | `NE | `PL | `VC | `VS ] Core_kernel.Bin_prot.Type_class.writer
val __bin_read_cond__ : 'a -> pos_ref:'b -> int -> [> `AL | `CC | `CS | `EQ | `GE | `GT | `HI | `LE | `LS | `LT | `MI | `NE | `PL | `VC | `VS ]
val bin_read_cond : Bin_prot.Common.buf -> pos_ref:Bin_prot.Common.pos_ref -> [> `AL | `CC | `CS | `EQ | `GE | `GT | `HI | `LE | `LS | `LT | `MI | `NE | `PL | `VC | `VS ]
val bin_reader_cond : [> `AL | `CC | `CS | `EQ | `GE | `GT | `HI | `LE | `LS | `LT | `MI | `NE | `PL | `VC | `VS ] Core_kernel.Bin_prot.Type_class.reader
val bin_cond : [ `AL | `CC | `CS | `EQ | `GE | `GT | `HI | `LE | `LS | `LT | `MI | `NE | `PL | `VC | `VS ] Core_kernel.Bin_prot.Type_class.t
val compare_cond : cond -> cond -> int
val __cond_of_sexp__ : Ppx_sexp_conv_lib.Sexp.t -> cond
val cond_of_sexp : Ppx_sexp_conv_lib.Sexp.t -> cond
val sexp_of_cond : cond -> Ppx_sexp_conv_lib.Sexp.t
val all_of_cond : cond list
type nil_reg = [
  1. | `Nil
]
val bin_shape_nil_reg : Core_kernel.Bin_prot.Shape.t
val bin_size_nil_reg : 'a -> int
val bin_write_nil_reg : Bin_prot.Common.buf -> pos:Bin_prot.Common.pos -> [< `Nil ] -> Bin_prot.Common.pos
val bin_writer_nil_reg : [< `Nil ] Core_kernel.Bin_prot.Type_class.writer
val __bin_read_nil_reg__ : 'a -> pos_ref:'b -> int -> [> `Nil ]
val bin_read_nil_reg : Bin_prot.Common.buf -> pos_ref:Bin_prot.Common.pos_ref -> [> `Nil ]
val bin_reader_nil_reg : [> `Nil ] Core_kernel.Bin_prot.Type_class.reader
val bin_nil_reg : [ `Nil ] Core_kernel.Bin_prot.Type_class.t
val compare_nil_reg : nil_reg -> nil_reg -> int
val __nil_reg_of_sexp__ : Ppx_sexp_conv_lib.Sexp.t -> nil_reg
val nil_reg_of_sexp : Ppx_sexp_conv_lib.Sexp.t -> nil_reg
val sexp_of_nil_reg : nil_reg -> Ppx_sexp_conv_lib.Sexp.t
val all_of_nil_reg : nil_reg list
type gpr_reg = [
  1. | `R0
  2. | `R1
  3. | `R2
  4. | `R3
  5. | `R4
  6. | `R5
  7. | `R6
  8. | `R7
  9. | `R8
  10. | `R9
  11. | `R10
  12. | `R11
  13. | `R12
  14. | `LR
  15. | `PC
  16. | `SP
]

General purpose registers

val bin_shape_gpr_reg : Core_kernel.Bin_prot.Shape.t
val bin_size_gpr_reg : 'a -> int
val bin_write_gpr_reg : Bin_prot.Common.buf -> pos:Bin_prot.Common.pos -> [< `LR | `PC | `R0 | `R1 | `R10 | `R11 | `R12 | `R2 | `R3 | `R4 | `R5 | `R6 | `R7 | `R8 | `R9 | `SP ] -> Bin_prot.Common.pos
val bin_writer_gpr_reg : [< `LR | `PC | `R0 | `R1 | `R10 | `R11 | `R12 | `R2 | `R3 | `R4 | `R5 | `R6 | `R7 | `R8 | `R9 | `SP ] Core_kernel.Bin_prot.Type_class.writer
val __bin_read_gpr_reg__ : 'a -> pos_ref:'b -> int -> [> `LR | `PC | `R0 | `R1 | `R10 | `R11 | `R12 | `R2 | `R3 | `R4 | `R5 | `R6 | `R7 | `R8 | `R9 | `SP ]
val bin_read_gpr_reg : Bin_prot.Common.buf -> pos_ref:Bin_prot.Common.pos_ref -> [> `LR | `PC | `R0 | `R1 | `R10 | `R11 | `R12 | `R2 | `R3 | `R4 | `R5 | `R6 | `R7 | `R8 | `R9 | `SP ]
val bin_reader_gpr_reg : [> `LR | `PC | `R0 | `R1 | `R10 | `R11 | `R12 | `R2 | `R3 | `R4 | `R5 | `R6 | `R7 | `R8 | `R9 | `SP ] Core_kernel.Bin_prot.Type_class.reader
val bin_gpr_reg : [ `LR | `PC | `R0 | `R1 | `R10 | `R11 | `R12 | `R2 | `R3 | `R4 | `R5 | `R6 | `R7 | `R8 | `R9 | `SP ] Core_kernel.Bin_prot.Type_class.t
val compare_gpr_reg : gpr_reg -> gpr_reg -> int
val __gpr_reg_of_sexp__ : Ppx_sexp_conv_lib.Sexp.t -> gpr_reg
val gpr_reg_of_sexp : Ppx_sexp_conv_lib.Sexp.t -> gpr_reg
val sexp_of_gpr_reg : gpr_reg -> Ppx_sexp_conv_lib.Sexp.t
val all_of_gpr_reg : gpr_reg list
type gpr_or_nil = [
  1. | nil_reg
  2. | gpr_reg
]
val bin_shape_gpr_or_nil : Core_kernel.Bin_prot.Shape.t
val bin_size_gpr_or_nil : [< `LR | `Nil | `PC | `R0 | `R1 | `R10 | `R11 | `R12 | `R2 | `R3 | `R4 | `R5 | `R6 | `R7 | `R8 | `R9 | `SP ] -> int
val bin_write_gpr_or_nil : Bin_prot.Common.buf -> pos:Bin_prot.Common.pos -> [< `LR | `Nil | `PC | `R0 | `R1 | `R10 | `R11 | `R12 | `R2 | `R3 | `R4 | `R5 | `R6 | `R7 | `R8 | `R9 | `SP ] -> Bin_prot.Common.pos
val bin_writer_gpr_or_nil : [< `LR | `Nil | `PC | `R0 | `R1 | `R10 | `R11 | `R12 | `R2 | `R3 | `R4 | `R5 | `R6 | `R7 | `R8 | `R9 | `SP ] Core_kernel.Bin_prot.Type_class.writer
val __bin_read_gpr_or_nil__ : 'a -> pos_ref:'b -> int -> gpr_or_nil
val bin_read_gpr_or_nil : Bin_prot.Common.buf -> pos_ref:Bin_prot.Common.pos_ref -> gpr_or_nil
val bin_reader_gpr_or_nil : gpr_or_nil Core_kernel.Bin_prot.Type_class.reader
val bin_gpr_or_nil : gpr_or_nil Core_kernel.Bin_prot.Type_class.t
val compare_gpr_or_nil : gpr_or_nil -> gpr_or_nil -> int
val __gpr_or_nil_of_sexp__ : Ppx_sexp_conv_lib.Sexp.t -> gpr_or_nil
val gpr_or_nil_of_sexp : Ppx_sexp_conv_lib.Sexp.t -> gpr_or_nil
val sexp_of_gpr_or_nil : gpr_or_nil -> Ppx_sexp_conv_lib.Sexp.t
val all_of_gpr_or_nil : gpr_or_nil list
type ccr_reg = [
  1. | `CPSR
  2. | `SPSR
  3. | `ITSTATE
]

conditition code registers

val bin_shape_ccr_reg : Core_kernel.Bin_prot.Shape.t
val bin_size_ccr_reg : 'a -> int
val bin_write_ccr_reg : Bin_prot.Common.buf -> pos:Bin_prot.Common.pos -> [< `CPSR | `ITSTATE | `SPSR ] -> Bin_prot.Common.pos
val bin_writer_ccr_reg : [< `CPSR | `ITSTATE | `SPSR ] Core_kernel.Bin_prot.Type_class.writer
val __bin_read_ccr_reg__ : 'a -> pos_ref:'b -> int -> [> `CPSR | `ITSTATE | `SPSR ]
val bin_read_ccr_reg : Bin_prot.Common.buf -> pos_ref:Bin_prot.Common.pos_ref -> [> `CPSR | `ITSTATE | `SPSR ]
val bin_reader_ccr_reg : [> `CPSR | `ITSTATE | `SPSR ] Core_kernel.Bin_prot.Type_class.reader
val bin_ccr_reg : [ `CPSR | `ITSTATE | `SPSR ] Core_kernel.Bin_prot.Type_class.t
val compare_ccr_reg : ccr_reg -> ccr_reg -> int
val __ccr_reg_of_sexp__ : Ppx_sexp_conv_lib.Sexp.t -> ccr_reg
val ccr_reg_of_sexp : Ppx_sexp_conv_lib.Sexp.t -> ccr_reg
val sexp_of_ccr_reg : ccr_reg -> Ppx_sexp_conv_lib.Sexp.t
val all_of_ccr_reg : ccr_reg list
type ccr_or_nil = [
  1. | nil_reg
  2. | ccr_reg
]
val bin_shape_ccr_or_nil : Core_kernel.Bin_prot.Shape.t
val bin_size_ccr_or_nil : [< `CPSR | `ITSTATE | `Nil | `SPSR ] -> int
val bin_write_ccr_or_nil : Bin_prot.Common.buf -> pos:Bin_prot.Common.pos -> [< `CPSR | `ITSTATE | `Nil | `SPSR ] -> Bin_prot.Common.pos
val bin_writer_ccr_or_nil : [< `CPSR | `ITSTATE | `Nil | `SPSR ] Core_kernel.Bin_prot.Type_class.writer
val __bin_read_ccr_or_nil__ : 'a -> pos_ref:'b -> int -> ccr_or_nil
val bin_read_ccr_or_nil : Bin_prot.Common.buf -> pos_ref:Bin_prot.Common.pos_ref -> ccr_or_nil
val bin_reader_ccr_or_nil : ccr_or_nil Core_kernel.Bin_prot.Type_class.reader
val bin_ccr_or_nil : ccr_or_nil Core_kernel.Bin_prot.Type_class.t
val compare_ccr_or_nil : ccr_or_nil -> ccr_or_nil -> int
val __ccr_or_nil_of_sexp__ : Ppx_sexp_conv_lib.Sexp.t -> ccr_or_nil
val ccr_or_nil_of_sexp : Ppx_sexp_conv_lib.Sexp.t -> ccr_or_nil
val sexp_of_ccr_or_nil : ccr_or_nil -> Ppx_sexp_conv_lib.Sexp.t
val all_of_ccr_or_nil : ccr_or_nil list
type non_nil_reg = [
  1. | gpr_reg
  2. | ccr_reg
]
val bin_shape_non_nil_reg : Core_kernel.Bin_prot.Shape.t
val bin_size_non_nil_reg : [< `CPSR | `ITSTATE | `LR | `PC | `R0 | `R1 | `R10 | `R11 | `R12 | `R2 | `R3 | `R4 | `R5 | `R6 | `R7 | `R8 | `R9 | `SP | `SPSR ] -> int
val bin_write_non_nil_reg : Bin_prot.Common.buf -> pos:Bin_prot.Common.pos -> [< `CPSR | `ITSTATE | `LR | `PC | `R0 | `R1 | `R10 | `R11 | `R12 | `R2 | `R3 | `R4 | `R5 | `R6 | `R7 | `R8 | `R9 | `SP | `SPSR ] -> Bin_prot.Common.pos
val bin_writer_non_nil_reg : [< `CPSR | `ITSTATE | `LR | `PC | `R0 | `R1 | `R10 | `R11 | `R12 | `R2 | `R3 | `R4 | `R5 | `R6 | `R7 | `R8 | `R9 | `SP | `SPSR ] Core_kernel.Bin_prot.Type_class.writer
val __bin_read_non_nil_reg__ : 'a -> pos_ref:'b -> int -> non_nil_reg
val bin_read_non_nil_reg : Bin_prot.Common.buf -> pos_ref:Bin_prot.Common.pos_ref -> non_nil_reg
val bin_reader_non_nil_reg : non_nil_reg Core_kernel.Bin_prot.Type_class.reader
val bin_non_nil_reg : non_nil_reg Core_kernel.Bin_prot.Type_class.t
val compare_non_nil_reg : non_nil_reg -> non_nil_reg -> int
val __non_nil_reg_of_sexp__ : Ppx_sexp_conv_lib.Sexp.t -> non_nil_reg
val non_nil_reg_of_sexp : Ppx_sexp_conv_lib.Sexp.t -> non_nil_reg
val sexp_of_non_nil_reg : non_nil_reg -> Ppx_sexp_conv_lib.Sexp.t
val all_of_non_nil_reg : non_nil_reg list
type reg = [
  1. | nil_reg
  2. | non_nil_reg
]
val bin_shape_reg : Core_kernel.Bin_prot.Shape.t
val bin_size_reg : [< `CPSR | `ITSTATE | `LR | `Nil | `PC | `R0 | `R1 | `R10 | `R11 | `R12 | `R2 | `R3 | `R4 | `R5 | `R6 | `R7 | `R8 | `R9 | `SP | `SPSR ] -> int
val bin_write_reg : Bin_prot.Common.buf -> pos:Bin_prot.Common.pos -> [< `CPSR | `ITSTATE | `LR | `Nil | `PC | `R0 | `R1 | `R10 | `R11 | `R12 | `R2 | `R3 | `R4 | `R5 | `R6 | `R7 | `R8 | `R9 | `SP | `SPSR ] -> Bin_prot.Common.pos
val bin_writer_reg : [< `CPSR | `ITSTATE | `LR | `Nil | `PC | `R0 | `R1 | `R10 | `R11 | `R12 | `R2 | `R3 | `R4 | `R5 | `R6 | `R7 | `R8 | `R9 | `SP | `SPSR ] Core_kernel.Bin_prot.Type_class.writer
val __bin_read_reg__ : 'a -> pos_ref:'b -> int -> reg
val bin_read_reg : Bin_prot.Common.buf -> pos_ref:Bin_prot.Common.pos_ref -> reg
val bin_reader_reg : reg Core_kernel.Bin_prot.Type_class.reader
val bin_reg : reg Core_kernel.Bin_prot.Type_class.t
val compare_reg : reg -> reg -> int
val __reg_of_sexp__ : Ppx_sexp_conv_lib.Sexp.t -> reg
val reg_of_sexp : Ppx_sexp_conv_lib.Sexp.t -> reg
val sexp_of_reg : reg -> Ppx_sexp_conv_lib.Sexp.t
val all_of_reg : reg list
type op = [
  1. | `Reg of reg
  2. | `Imm of Bap.Std.word
]
val bin_shape_op : Core_kernel.Bin_prot.Shape.t
val bin_size_op : [< `Imm of Bap.Std.word | `Reg of [< `CPSR | `ITSTATE | `LR | `Nil | `PC | `R0 | `R1 | `R10 | `R11 | `R12 | `R2 | `R3 | `R4 | `R5 | `R6 | `R7 | `R8 | `R9 | `SP | `SPSR ] ] -> int
val bin_write_op : Bin_prot.Common.buf -> pos:Bin_prot.Common.pos -> [< `Imm of Bap.Std.word | `Reg of [< `CPSR | `ITSTATE | `LR | `Nil | `PC | `R0 | `R1 | `R10 | `R11 | `R12 | `R2 | `R3 | `R4 | `R5 | `R6 | `R7 | `R8 | `R9 | `SP | `SPSR ] ] -> Bin_prot.Common.pos
val bin_writer_op : [< `Imm of Bap.Std.word & Bap.Std.word | `Reg of [< `CPSR | `ITSTATE | `LR | `Nil | `PC | `R0 | `R1 | `R10 | `R11 | `R12 | `R2 | `R3 | `R4 | `R5 | `R6 | `R7 | `R8 | `R9 | `SP | `SPSR ] & [< `CPSR | `ITSTATE | `LR | `Nil | `PC | `R0 | `R1 | `R10 | `R11 | `R12 | `R2 | `R3 | `R4 | `R5 | `R6 | `R7 | `R8 | `R9 | `SP | `SPSR ] ] Core_kernel.Bin_prot.Type_class.writer
val __bin_read_op__ : Bin_prot.Common.buf -> pos_ref:Bin_prot.Common.pos_ref -> int -> [> `Imm of Bap.Std.word | `Reg of reg ]
val bin_read_op : Bin_prot.Common.buf -> pos_ref:Bin_prot.Common.pos_ref -> [> `Imm of Bap.Std.word | `Reg of reg ]
val bin_reader_op : [> `Imm of Bap.Std.word | `Reg of reg ] Core_kernel.Bin_prot.Type_class.reader
val bin_op : [ `Imm of Bap.Std.word | `Reg of reg ] Core_kernel.Bin_prot.Type_class.t
val compare_op : op -> op -> int
val __op_of_sexp__ : Ppx_sexp_conv_lib.Sexp.t -> op
val op_of_sexp : Ppx_sexp_conv_lib.Sexp.t -> op
val sexp_of_op : op -> Ppx_sexp_conv_lib.Sexp.t
type move_insn = [
  1. | `ADCri
  2. | `ADCrr
  3. | `ADCrsi
  4. | `ADCrsr
  5. | `ADDri
  6. | `ADDrr
  7. | `ADDrsi
  8. | `ADDrsr
  9. | `ANDri
  10. | `ANDrr
  11. | `ANDrsi
  12. | `ANDrsr
  13. | `BICri
  14. | `BICrr
  15. | `BICrsi
  16. | `BICrsr
  17. | `CMNri
  18. | `CMNzrr
  19. | `CMNzrsi
  20. | `CMNzrsr
  21. | `CMPri
  22. | `CMPrr
  23. | `CMPrsi
  24. | `CMPrsr
  25. | `EORri
  26. | `EORrr
  27. | `EORrsi
  28. | `EORrsr
  29. | `MOVTi16
  30. | `MOVi
  31. | `MOVi16
  32. | `MOVr
  33. | `MOVsi
  34. | `MOVsr
  35. | `MOVPCLR
  36. | `MVNi
  37. | `MVNr
  38. | `MVNsi
  39. | `MVNsr
  40. | `ORRri
  41. | `ORRrr
  42. | `ORRrsi
  43. | `ORRrsr
  44. | `RSBri
  45. | `RSBrr
  46. | `RSBrsi
  47. | `RSBrsr
  48. | `RSCri
  49. | `RSCrr
  50. | `RSCrsi
  51. | `RSCrsr
  52. | `SBCri
  53. | `SBCrr
  54. | `SBCrsi
  55. | `SBCrsr
  56. | `SUBri
  57. | `SUBrr
  58. | `SUBrsi
  59. | `SUBrsr
  60. | `TEQri
  61. | `TEQrr
  62. | `TEQrsi
  63. | `TEQrsr
  64. | `TSTri
  65. | `TSTrr
  66. | `TSTrsi
  67. | `TSTrsr
]
val bin_shape_move_insn : Core_kernel.Bin_prot.Shape.t
val bin_size_move_insn : 'a -> int
val bin_write_move_insn : Bin_prot.Common.buf -> pos:Bin_prot.Common.pos -> [< `ADCri | `ADCrr | `ADCrsi | `ADCrsr | `ADDri | `ADDrr | `ADDrsi | `ADDrsr | `ANDri | `ANDrr | `ANDrsi | `ANDrsr | `BICri | `BICrr | `BICrsi | `BICrsr | `CMNri | `CMNzrr | `CMNzrsi | `CMNzrsr | `CMPri | `CMPrr | `CMPrsi | `CMPrsr | `EORri | `EORrr | `EORrsi | `EORrsr | `MOVPCLR | `MOVTi16 | `MOVi | `MOVi16 | `MOVr | `MOVsi | `MOVsr | `MVNi | `MVNr | `MVNsi | `MVNsr | `ORRri | `ORRrr | `ORRrsi | `ORRrsr | `RSBri | `RSBrr | `RSBrsi | `RSBrsr | `RSCri | `RSCrr | `RSCrsi | `RSCrsr | `SBCri | `SBCrr | `SBCrsi | `SBCrsr | `SUBri | `SUBrr | `SUBrsi | `SUBrsr | `TEQri | `TEQrr | `TEQrsi | `TEQrsr | `TSTri | `TSTrr | `TSTrsi | `TSTrsr ] -> Bin_prot.Common.pos
val bin_writer_move_insn : [< `ADCri | `ADCrr | `ADCrsi | `ADCrsr | `ADDri | `ADDrr | `ADDrsi | `ADDrsr | `ANDri | `ANDrr | `ANDrsi | `ANDrsr | `BICri | `BICrr | `BICrsi | `BICrsr | `CMNri | `CMNzrr | `CMNzrsi | `CMNzrsr | `CMPri | `CMPrr | `CMPrsi | `CMPrsr | `EORri | `EORrr | `EORrsi | `EORrsr | `MOVPCLR | `MOVTi16 | `MOVi | `MOVi16 | `MOVr | `MOVsi | `MOVsr | `MVNi | `MVNr | `MVNsi | `MVNsr | `ORRri | `ORRrr | `ORRrsi | `ORRrsr | `RSBri | `RSBrr | `RSBrsi | `RSBrsr | `RSCri | `RSCrr | `RSCrsi | `RSCrsr | `SBCri | `SBCrr | `SBCrsi | `SBCrsr | `SUBri | `SUBrr | `SUBrsi | `SUBrsr | `TEQri | `TEQrr | `TEQrsi | `TEQrsr | `TSTri | `TSTrr | `TSTrsi | `TSTrsr ] Core_kernel.Bin_prot.Type_class.writer
val __bin_read_move_insn__ : 'a -> pos_ref:'b -> int -> [> `ADCri | `ADCrr | `ADCrsi | `ADCrsr | `ADDri | `ADDrr | `ADDrsi | `ADDrsr | `ANDri | `ANDrr | `ANDrsi | `ANDrsr | `BICri | `BICrr | `BICrsi | `BICrsr | `CMNri | `CMNzrr | `CMNzrsi | `CMNzrsr | `CMPri | `CMPrr | `CMPrsi | `CMPrsr | `EORri | `EORrr | `EORrsi | `EORrsr | `MOVPCLR | `MOVTi16 | `MOVi | `MOVi16 | `MOVr | `MOVsi | `MOVsr | `MVNi | `MVNr | `MVNsi | `MVNsr | `ORRri | `ORRrr | `ORRrsi | `ORRrsr | `RSBri | `RSBrr | `RSBrsi | `RSBrsr | `RSCri | `RSCrr | `RSCrsi | `RSCrsr | `SBCri | `SBCrr | `SBCrsi | `SBCrsr | `SUBri | `SUBrr | `SUBrsi | `SUBrsr | `TEQri | `TEQrr | `TEQrsi | `TEQrsr | `TSTri | `TSTrr | `TSTrsi | `TSTrsr ]
val bin_read_move_insn : Bin_prot.Common.buf -> pos_ref:Bin_prot.Common.pos_ref -> [> `ADCri | `ADCrr | `ADCrsi | `ADCrsr | `ADDri | `ADDrr | `ADDrsi | `ADDrsr | `ANDri | `ANDrr | `ANDrsi | `ANDrsr | `BICri | `BICrr | `BICrsi | `BICrsr | `CMNri | `CMNzrr | `CMNzrsi | `CMNzrsr | `CMPri | `CMPrr | `CMPrsi | `CMPrsr | `EORri | `EORrr | `EORrsi | `EORrsr | `MOVPCLR | `MOVTi16 | `MOVi | `MOVi16 | `MOVr | `MOVsi | `MOVsr | `MVNi | `MVNr | `MVNsi | `MVNsr | `ORRri | `ORRrr | `ORRrsi | `ORRrsr | `RSBri | `RSBrr | `RSBrsi | `RSBrsr | `RSCri | `RSCrr | `RSCrsi | `RSCrsr | `SBCri | `SBCrr | `SBCrsi | `SBCrsr | `SUBri | `SUBrr | `SUBrsi | `SUBrsr | `TEQri | `TEQrr | `TEQrsi | `TEQrsr | `TSTri | `TSTrr | `TSTrsi | `TSTrsr ]
val bin_reader_move_insn : [> `ADCri | `ADCrr | `ADCrsi | `ADCrsr | `ADDri | `ADDrr | `ADDrsi | `ADDrsr | `ANDri | `ANDrr | `ANDrsi | `ANDrsr | `BICri | `BICrr | `BICrsi | `BICrsr | `CMNri | `CMNzrr | `CMNzrsi | `CMNzrsr | `CMPri | `CMPrr | `CMPrsi | `CMPrsr | `EORri | `EORrr | `EORrsi | `EORrsr | `MOVPCLR | `MOVTi16 | `MOVi | `MOVi16 | `MOVr | `MOVsi | `MOVsr | `MVNi | `MVNr | `MVNsi | `MVNsr | `ORRri | `ORRrr | `ORRrsi | `ORRrsr | `RSBri | `RSBrr | `RSBrsi | `RSBrsr | `RSCri | `RSCrr | `RSCrsi | `RSCrsr | `SBCri | `SBCrr | `SBCrsi | `SBCrsr | `SUBri | `SUBrr | `SUBrsi | `SUBrsr | `TEQri | `TEQrr | `TEQrsi | `TEQrsr | `TSTri | `TSTrr | `TSTrsi | `TSTrsr ] Core_kernel.Bin_prot.Type_class.reader
val bin_move_insn : [ `ADCri | `ADCrr | `ADCrsi | `ADCrsr | `ADDri | `ADDrr | `ADDrsi | `ADDrsr | `ANDri | `ANDrr | `ANDrsi | `ANDrsr | `BICri | `BICrr | `BICrsi | `BICrsr | `CMNri | `CMNzrr | `CMNzrsi | `CMNzrsr | `CMPri | `CMPrr | `CMPrsi | `CMPrsr | `EORri | `EORrr | `EORrsi | `EORrsr | `MOVPCLR | `MOVTi16 | `MOVi | `MOVi16 | `MOVr | `MOVsi | `MOVsr | `MVNi | `MVNr | `MVNsi | `MVNsr | `ORRri | `ORRrr | `ORRrsi | `ORRrsr | `RSBri | `RSBrr | `RSBrsi | `RSBrsr | `RSCri | `RSCrr | `RSCrsi | `RSCrsr | `SBCri | `SBCrr | `SBCrsi | `SBCrsr | `SUBri | `SUBrr | `SUBrsi | `SUBrsr | `TEQri | `TEQrr | `TEQrsi | `TEQrsr | `TSTri | `TSTrr | `TSTrsi | `TSTrsr ] Core_kernel.Bin_prot.Type_class.t
val compare_move_insn : move_insn -> move_insn -> int
val __move_insn_of_sexp__ : Ppx_sexp_conv_lib.Sexp.t -> move_insn
val move_insn_of_sexp : Ppx_sexp_conv_lib.Sexp.t -> move_insn
val sexp_of_move_insn : move_insn -> Ppx_sexp_conv_lib.Sexp.t
val all_of_move_insn : move_insn list
type bits_insn = [
  1. | `BFC
  2. | `BFI
  3. | `PKHTB
  4. | `RBIT
  5. | `SBFX
  6. | `SWPB
  7. | `SXTAB
  8. | `SXTAH
  9. | `SXTB
  10. | `SXTH
  11. | `UBFX
  12. | `UXTAB
  13. | `UXTAH
  14. | `UXTB
  15. | `UXTH
  16. | `REV
  17. | `REV16
]
val bin_shape_bits_insn : Core_kernel.Bin_prot.Shape.t
val bin_size_bits_insn : 'a -> int
val bin_write_bits_insn : Bin_prot.Common.buf -> pos:Bin_prot.Common.pos -> [< `BFC | `BFI | `PKHTB | `RBIT | `REV | `REV16 | `SBFX | `SWPB | `SXTAB | `SXTAH | `SXTB | `SXTH | `UBFX | `UXTAB | `UXTAH | `UXTB | `UXTH ] -> Bin_prot.Common.pos
val bin_writer_bits_insn : [< `BFC | `BFI | `PKHTB | `RBIT | `REV | `REV16 | `SBFX | `SWPB | `SXTAB | `SXTAH | `SXTB | `SXTH | `UBFX | `UXTAB | `UXTAH | `UXTB | `UXTH ] Core_kernel.Bin_prot.Type_class.writer
val __bin_read_bits_insn__ : 'a -> pos_ref:'b -> int -> [> `BFC | `BFI | `PKHTB | `RBIT | `REV | `REV16 | `SBFX | `SWPB | `SXTAB | `SXTAH | `SXTB | `SXTH | `UBFX | `UXTAB | `UXTAH | `UXTB | `UXTH ]
val bin_read_bits_insn : Bin_prot.Common.buf -> pos_ref:Bin_prot.Common.pos_ref -> [> `BFC | `BFI | `PKHTB | `RBIT | `REV | `REV16 | `SBFX | `SWPB | `SXTAB | `SXTAH | `SXTB | `SXTH | `UBFX | `UXTAB | `UXTAH | `UXTB | `UXTH ]
val bin_reader_bits_insn : [> `BFC | `BFI | `PKHTB | `RBIT | `REV | `REV16 | `SBFX | `SWPB | `SXTAB | `SXTAH | `SXTB | `SXTH | `UBFX | `UXTAB | `UXTAH | `UXTB | `UXTH ] Core_kernel.Bin_prot.Type_class.reader
val bin_bits_insn : [ `BFC | `BFI | `PKHTB | `RBIT | `REV | `REV16 | `SBFX | `SWPB | `SXTAB | `SXTAH | `SXTB | `SXTH | `UBFX | `UXTAB | `UXTAH | `UXTB | `UXTH ] Core_kernel.Bin_prot.Type_class.t
val compare_bits_insn : bits_insn -> bits_insn -> int
val __bits_insn_of_sexp__ : Ppx_sexp_conv_lib.Sexp.t -> bits_insn
val bits_insn_of_sexp : Ppx_sexp_conv_lib.Sexp.t -> bits_insn
val sexp_of_bits_insn : bits_insn -> Ppx_sexp_conv_lib.Sexp.t
val all_of_bits_insn : bits_insn list
type mult_insn = [
  1. | `MLA
  2. | `MLS
  3. | `MUL
  4. | `SMLABB
  5. | `SMLAD
  6. | `SMLAL
  7. | `SMLALBT
  8. | `SMLAWB
  9. | `SMUAD
  10. | `SMULBB
  11. | `SMULL
  12. | `SMULTB
  13. | `UMLAL
  14. | `UMULL
]
val bin_shape_mult_insn : Core_kernel.Bin_prot.Shape.t
val bin_size_mult_insn : 'a -> int
val bin_write_mult_insn : Bin_prot.Common.buf -> pos:Bin_prot.Common.pos -> [< `MLA | `MLS | `MUL | `SMLABB | `SMLAD | `SMLAL | `SMLALBT | `SMLAWB | `SMUAD | `SMULBB | `SMULL | `SMULTB | `UMLAL | `UMULL ] -> Bin_prot.Common.pos
val bin_writer_mult_insn : [< `MLA | `MLS | `MUL | `SMLABB | `SMLAD | `SMLAL | `SMLALBT | `SMLAWB | `SMUAD | `SMULBB | `SMULL | `SMULTB | `UMLAL | `UMULL ] Core_kernel.Bin_prot.Type_class.writer
val __bin_read_mult_insn__ : 'a -> pos_ref:'b -> int -> [> `MLA | `MLS | `MUL | `SMLABB | `SMLAD | `SMLAL | `SMLALBT | `SMLAWB | `SMUAD | `SMULBB | `SMULL | `SMULTB | `UMLAL | `UMULL ]
val bin_read_mult_insn : Bin_prot.Common.buf -> pos_ref:Bin_prot.Common.pos_ref -> [> `MLA | `MLS | `MUL | `SMLABB | `SMLAD | `SMLAL | `SMLALBT | `SMLAWB | `SMUAD | `SMULBB | `SMULL | `SMULTB | `UMLAL | `UMULL ]
val bin_reader_mult_insn : [> `MLA | `MLS | `MUL | `SMLABB | `SMLAD | `SMLAL | `SMLALBT | `SMLAWB | `SMUAD | `SMULBB | `SMULL | `SMULTB | `UMLAL | `UMULL ] Core_kernel.Bin_prot.Type_class.reader
val bin_mult_insn : [ `MLA | `MLS | `MUL | `SMLABB | `SMLAD | `SMLAL | `SMLALBT | `SMLAWB | `SMUAD | `SMULBB | `SMULL | `SMULTB | `UMLAL | `UMULL ] Core_kernel.Bin_prot.Type_class.t
val compare_mult_insn : mult_insn -> mult_insn -> int
val __mult_insn_of_sexp__ : Ppx_sexp_conv_lib.Sexp.t -> mult_insn
val mult_insn_of_sexp : Ppx_sexp_conv_lib.Sexp.t -> mult_insn
val sexp_of_mult_insn : mult_insn -> Ppx_sexp_conv_lib.Sexp.t
val all_of_mult_insn : mult_insn list
type mem_multi_insn = [
  1. | `LDMDA
  2. | `LDMDA_UPD
  3. | `LDMDB
  4. | `LDMDB_UPD
  5. | `LDMIA
  6. | `LDMIA_UPD
  7. | `LDMIB
  8. | `LDMIB_UPD
  9. | `STMDA
  10. | `STMDA_UPD
  11. | `STMDB
  12. | `STMDB_UPD
  13. | `STMIA
  14. | `STMIA_UPD
  15. | `STMIB
  16. | `STMIB_UPD
]
val bin_shape_mem_multi_insn : Core_kernel.Bin_prot.Shape.t
val bin_size_mem_multi_insn : 'a -> int
val bin_write_mem_multi_insn : Bin_prot.Common.buf -> pos:Bin_prot.Common.pos -> [< `LDMDA | `LDMDA_UPD | `LDMDB | `LDMDB_UPD | `LDMIA | `LDMIA_UPD | `LDMIB | `LDMIB_UPD | `STMDA | `STMDA_UPD | `STMDB | `STMDB_UPD | `STMIA | `STMIA_UPD | `STMIB | `STMIB_UPD ] -> Bin_prot.Common.pos
val bin_writer_mem_multi_insn : [< `LDMDA | `LDMDA_UPD | `LDMDB | `LDMDB_UPD | `LDMIA | `LDMIA_UPD | `LDMIB | `LDMIB_UPD | `STMDA | `STMDA_UPD | `STMDB | `STMDB_UPD | `STMIA | `STMIA_UPD | `STMIB | `STMIB_UPD ] Core_kernel.Bin_prot.Type_class.writer
val __bin_read_mem_multi_insn__ : 'a -> pos_ref:'b -> int -> [> `LDMDA | `LDMDA_UPD | `LDMDB | `LDMDB_UPD | `LDMIA | `LDMIA_UPD | `LDMIB | `LDMIB_UPD | `STMDA | `STMDA_UPD | `STMDB | `STMDB_UPD | `STMIA | `STMIA_UPD | `STMIB | `STMIB_UPD ]
val bin_read_mem_multi_insn : Bin_prot.Common.buf -> pos_ref:Bin_prot.Common.pos_ref -> [> `LDMDA | `LDMDA_UPD | `LDMDB | `LDMDB_UPD | `LDMIA | `LDMIA_UPD | `LDMIB | `LDMIB_UPD | `STMDA | `STMDA_UPD | `STMDB | `STMDB_UPD | `STMIA | `STMIA_UPD | `STMIB | `STMIB_UPD ]
val bin_reader_mem_multi_insn : [> `LDMDA | `LDMDA_UPD | `LDMDB | `LDMDB_UPD | `LDMIA | `LDMIA_UPD | `LDMIB | `LDMIB_UPD | `STMDA | `STMDA_UPD | `STMDB | `STMDB_UPD | `STMIA | `STMIA_UPD | `STMIB | `STMIB_UPD ] Core_kernel.Bin_prot.Type_class.reader
val bin_mem_multi_insn : [ `LDMDA | `LDMDA_UPD | `LDMDB | `LDMDB_UPD | `LDMIA | `LDMIA_UPD | `LDMIB | `LDMIB_UPD | `STMDA | `STMDA_UPD | `STMDB | `STMDB_UPD | `STMIA | `STMIA_UPD | `STMIB | `STMIB_UPD ] Core_kernel.Bin_prot.Type_class.t
val compare_mem_multi_insn : mem_multi_insn -> mem_multi_insn -> int
val __mem_multi_insn_of_sexp__ : Ppx_sexp_conv_lib.Sexp.t -> mem_multi_insn
val mem_multi_insn_of_sexp : Ppx_sexp_conv_lib.Sexp.t -> mem_multi_insn
val sexp_of_mem_multi_insn : mem_multi_insn -> Ppx_sexp_conv_lib.Sexp.t
val all_of_mem_multi_insn : mem_multi_insn list
type mem_insn = [
  1. | mem_multi_insn
  2. | `LDRBT_POST_IMM
  3. | `LDRBT_POST_REG
  4. | `LDRB_POST_IMM
  5. | `LDRB_POST_REG
  6. | `LDRB_PRE_IMM
  7. | `LDRB_PRE_REG
  8. | `LDRBi12
  9. | `LDRBrs
  10. | `LDRD
  11. | `LDRD_POST
  12. | `LDRD_PRE
  13. | `LDREX
  14. | `LDREXB
  15. | `LDREXD
  16. | `LDREXH
  17. | `LDRH
  18. | `LDRHTr
  19. | `LDRH_POST
  20. | `LDRH_PRE
  21. | `LDRSB
  22. | `LDRSBTr
  23. | `LDRSB_POST
  24. | `LDRSB_PRE
  25. | `LDRSH
  26. | `LDRSHTi
  27. | `LDRSHTr
  28. | `LDRSH_POST
  29. | `LDRSH_PRE
  30. | `LDRT_POST_REG
  31. | `LDR_POST_IMM
  32. | `LDR_POST_REG
  33. | `LDR_PRE_IMM
  34. | `LDR_PRE_REG
  35. | `LDRi12
  36. | `LDRrs
  37. | `STRBT_POST_IMM
  38. | `STRBT_POST_REG
  39. | `STRB_POST_IMM
  40. | `STRB_POST_REG
  41. | `STRB_PRE_IMM
  42. | `STRB_PRE_REG
  43. | `STRBi12
  44. | `STRBrs
  45. | `STRD
  46. | `STRD_POST
  47. | `STRD_PRE
  48. | `STREX
  49. | `STREXB
  50. | `STREXD
  51. | `STREXH
  52. | `STRH
  53. | `STRHTr
  54. | `STRH_POST
  55. | `STRH_PRE
  56. | `STRT_POST_REG
  57. | `STR_POST_IMM
  58. | `STR_POST_REG
  59. | `STR_PRE_IMM
  60. | `STR_PRE_REG
  61. | `STRi12
  62. | `STRrs
]
val bin_shape_mem_insn : Core_kernel.Bin_prot.Shape.t
val bin_size_mem_insn : [> mem_multi_insn ] -> int
val bin_write_mem_insn : Bin_prot.Common.buf -> pos:Bin_prot.Common.pos -> [< `LDMDA | `LDMDA_UPD | `LDMDB | `LDMDB_UPD | `LDMIA | `LDMIA_UPD | `LDMIB | `LDMIB_UPD | `LDRBT_POST_IMM | `LDRBT_POST_REG | `LDRB_POST_IMM | `LDRB_POST_REG | `LDRB_PRE_IMM | `LDRB_PRE_REG | `LDRBi12 | `LDRBrs | `LDRD | `LDRD_POST | `LDRD_PRE | `LDREX | `LDREXB | `LDREXD | `LDREXH | `LDRH | `LDRHTr | `LDRH_POST | `LDRH_PRE | `LDRSB | `LDRSBTr | `LDRSB_POST | `LDRSB_PRE | `LDRSH | `LDRSHTi | `LDRSHTr | `LDRSH_POST | `LDRSH_PRE | `LDRT_POST_REG | `LDR_POST_IMM | `LDR_POST_REG | `LDR_PRE_IMM | `LDR_PRE_REG | `LDRi12 | `LDRrs | `STMDA | `STMDA_UPD | `STMDB | `STMDB_UPD | `STMIA | `STMIA_UPD | `STMIB | `STMIB_UPD | `STRBT_POST_IMM | `STRBT_POST_REG | `STRB_POST_IMM | `STRB_POST_REG | `STRB_PRE_IMM | `STRB_PRE_REG | `STRBi12 | `STRBrs | `STRD | `STRD_POST | `STRD_PRE | `STREX | `STREXB | `STREXD | `STREXH | `STRH | `STRHTr | `STRH_POST | `STRH_PRE | `STRT_POST_REG | `STR_POST_IMM | `STR_POST_REG | `STR_PRE_IMM | `STR_PRE_REG | `STRi12 | `STRrs ] -> Bin_prot.Common.pos
val bin_writer_mem_insn : [< `LDMDA | `LDMDA_UPD | `LDMDB | `LDMDB_UPD | `LDMIA | `LDMIA_UPD | `LDMIB | `LDMIB_UPD | `LDRBT_POST_IMM | `LDRBT_POST_REG | `LDRB_POST_IMM | `LDRB_POST_REG | `LDRB_PRE_IMM | `LDRB_PRE_REG | `LDRBi12 | `LDRBrs | `LDRD | `LDRD_POST | `LDRD_PRE | `LDREX | `LDREXB | `LDREXD | `LDREXH | `LDRH | `LDRHTr | `LDRH_POST | `LDRH_PRE | `LDRSB | `LDRSBTr | `LDRSB_POST | `LDRSB_PRE | `LDRSH | `LDRSHTi | `LDRSHTr | `LDRSH_POST | `LDRSH_PRE | `LDRT_POST_REG | `LDR_POST_IMM | `LDR_POST_REG | `LDR_PRE_IMM | `LDR_PRE_REG | `LDRi12 | `LDRrs | `STMDA | `STMDA_UPD | `STMDB | `STMDB_UPD | `STMIA | `STMIA_UPD | `STMIB | `STMIB_UPD | `STRBT_POST_IMM | `STRBT_POST_REG | `STRB_POST_IMM | `STRB_POST_REG | `STRB_PRE_IMM | `STRB_PRE_REG | `STRBi12 | `STRBrs | `STRD | `STRD_POST | `STRD_PRE | `STREX | `STREXB | `STREXD | `STREXH | `STRH | `STRHTr | `STRH_POST | `STRH_PRE | `STRT_POST_REG | `STR_POST_IMM | `STR_POST_REG | `STR_PRE_IMM | `STR_PRE_REG | `STRi12 | `STRrs LDMDA LDMDA_UPD LDMDB LDMDB_UPD LDMIA LDMIA_UPD LDMIB LDMIB_UPD STMDA STMDA_UPD STMDB STMDB_UPD STMIA STMIA_UPD STMIB STMIB_UPD ] Core_kernel.Bin_prot.Type_class.writer
val __bin_read_mem_insn__ : 'a -> pos_ref:'b -> int -> mem_insn
val bin_read_mem_insn : Bin_prot.Common.buf -> pos_ref:Bin_prot.Common.pos_ref -> mem_insn
val bin_reader_mem_insn : mem_insn Core_kernel.Bin_prot.Type_class.reader
val bin_mem_insn : mem_insn Core_kernel.Bin_prot.Type_class.t
val compare_mem_insn : mem_insn -> mem_insn -> int
val __mem_insn_of_sexp__ : Ppx_sexp_conv_lib.Sexp.t -> mem_insn
val mem_insn_of_sexp : Ppx_sexp_conv_lib.Sexp.t -> mem_insn
val sexp_of_mem_insn : mem_insn -> Ppx_sexp_conv_lib.Sexp.t
val all_of_mem_insn : mem_insn list
type branch_insn = [
  1. | `BL
  2. | `BLX
  3. | `BLX_pred
  4. | `BLXi
  5. | `BL_pred
  6. | `BX
  7. | `BX_RET
  8. | `BX_pred
  9. | `Bcc
]
val bin_shape_branch_insn : Core_kernel.Bin_prot.Shape.t
val bin_size_branch_insn : 'a -> int
val bin_write_branch_insn : Bin_prot.Common.buf -> pos:Bin_prot.Common.pos -> [< `BL | `BLX | `BLX_pred | `BLXi | `BL_pred | `BX | `BX_RET | `BX_pred | `Bcc ] -> Bin_prot.Common.pos
val bin_writer_branch_insn : [< `BL | `BLX | `BLX_pred | `BLXi | `BL_pred | `BX | `BX_RET | `BX_pred | `Bcc ] Core_kernel.Bin_prot.Type_class.writer
val __bin_read_branch_insn__ : 'a -> pos_ref:'b -> int -> [> `BL | `BLX | `BLX_pred | `BLXi | `BL_pred | `BX | `BX_RET | `BX_pred | `Bcc ]
val bin_read_branch_insn : Bin_prot.Common.buf -> pos_ref:Bin_prot.Common.pos_ref -> [> `BL | `BLX | `BLX_pred | `BLXi | `BL_pred | `BX | `BX_RET | `BX_pred | `Bcc ]
val bin_reader_branch_insn : [> `BL | `BLX | `BLX_pred | `BLXi | `BL_pred | `BX | `BX_RET | `BX_pred | `Bcc ] Core_kernel.Bin_prot.Type_class.reader
val bin_branch_insn : [ `BL | `BLX | `BLX_pred | `BLXi | `BL_pred | `BX | `BX_RET | `BX_pred | `Bcc ] Core_kernel.Bin_prot.Type_class.t
val compare_branch_insn : branch_insn -> branch_insn -> int
val __branch_insn_of_sexp__ : Ppx_sexp_conv_lib.Sexp.t -> branch_insn
val branch_insn_of_sexp : Ppx_sexp_conv_lib.Sexp.t -> branch_insn
val sexp_of_branch_insn : branch_insn -> Ppx_sexp_conv_lib.Sexp.t
val all_of_branch_insn : branch_insn list
type special_insn = [
  1. | `CPS2p
  2. | `DMB
  3. | `DSB
  4. | `HINT
  5. | `MRS
  6. | `MSR
  7. | `PLDi12
  8. | `SVC
]
val bin_shape_special_insn : Core_kernel.Bin_prot.Shape.t
val bin_size_special_insn : 'a -> int
val bin_write_special_insn : Bin_prot.Common.buf -> pos:Bin_prot.Common.pos -> [< `CPS2p | `DMB | `DSB | `HINT | `MRS | `MSR | `PLDi12 | `SVC ] -> Bin_prot.Common.pos
val bin_writer_special_insn : [< `CPS2p | `DMB | `DSB | `HINT | `MRS | `MSR | `PLDi12 | `SVC ] Core_kernel.Bin_prot.Type_class.writer
val __bin_read_special_insn__ : 'a -> pos_ref:'b -> int -> [> `CPS2p | `DMB | `DSB | `HINT | `MRS | `MSR | `PLDi12 | `SVC ]
val bin_read_special_insn : Bin_prot.Common.buf -> pos_ref:Bin_prot.Common.pos_ref -> [> `CPS2p | `DMB | `DSB | `HINT | `MRS | `MSR | `PLDi12 | `SVC ]
val bin_reader_special_insn : [> `CPS2p | `DMB | `DSB | `HINT | `MRS | `MSR | `PLDi12 | `SVC ] Core_kernel.Bin_prot.Type_class.reader
val bin_special_insn : [ `CPS2p | `DMB | `DSB | `HINT | `MRS | `MSR | `PLDi12 | `SVC ] Core_kernel.Bin_prot.Type_class.t
val compare_special_insn : special_insn -> special_insn -> int
val __special_insn_of_sexp__ : Ppx_sexp_conv_lib.Sexp.t -> special_insn
val special_insn_of_sexp : Ppx_sexp_conv_lib.Sexp.t -> special_insn
val sexp_of_special_insn : special_insn -> Ppx_sexp_conv_lib.Sexp.t
val all_of_special_insn : special_insn list
val bin_shape_insn : Core_kernel.Bin_prot.Shape.t
val bin_size_insn : [< `ADCri | `ADCrr | `ADCrsi | `ADCrsr | `ADDri | `ADDrr | `ADDrsi | `ADDrsr | `ANDri | `ANDrr | `ANDrsi | `ANDrsr | `BFC | `BFI | `BICri | `BICrr | `BICrsi | `BICrsr | `BL | `BLX | `BLX_pred | `BLXi | `BL_pred | `BX | `BX_RET | `BX_pred | `Bcc | `CMNri | `CMNzrr | `CMNzrsi | `CMNzrsr | `CMPri | `CMPrr | `CMPrsi | `CMPrsr | `CPS2p | `DMB | `DSB | `EORri | `EORrr | `EORrsi | `EORrsr | `HINT | `LDMDA | `LDMDA_UPD | `LDMDB | `LDMDB_UPD | `LDMIA | `LDMIA_UPD | `LDMIB | `LDMIB_UPD | `LDRBT_POST_IMM | `LDRBT_POST_REG | `LDRB_POST_IMM | `LDRB_POST_REG | `LDRB_PRE_IMM | `LDRB_PRE_REG | `LDRBi12 | `LDRBrs | `LDRD | `LDRD_POST | `LDRD_PRE | `LDREX | `LDREXB | `LDREXD | `LDREXH | `LDRH | `LDRHTr | `LDRH_POST | `LDRH_PRE | `LDRSB | `LDRSBTr | `LDRSB_POST | `LDRSB_PRE | `LDRSH | `LDRSHTi | `LDRSHTr | `LDRSH_POST | `LDRSH_PRE | `LDRT_POST_REG | `LDR_POST_IMM | `LDR_POST_REG | `LDR_PRE_IMM | `LDR_PRE_REG | `LDRi12 | `LDRrs | `MLA | `MLS | `MOVPCLR | `MOVTi16 | `MOVi | `MOVi16 | `MOVr | `MOVsi | `MOVsr | `MRS | `MSR | `MUL | `MVNi | `MVNr | `MVNsi | `MVNsr | `ORRri | `ORRrr | `ORRrsi | `ORRrsr | `PKHTB | `PLDi12 | `RBIT | `REV | `REV16 | `RSBri | `RSBrr | `RSBrsi | `RSBrsr | `RSCri | `RSCrr | `RSCrsi | `RSCrsr | `SBCri | `SBCrr | `SBCrsi | `SBCrsr | `SBFX | `SMLABB | `SMLAD | `SMLAL | `SMLALBT | `SMLAWB | `SMUAD | `SMULBB | `SMULL | `SMULTB | `STMDA | `STMDA_UPD | `STMDB | `STMDB_UPD | `STMIA | `STMIA_UPD | `STMIB | `STMIB_UPD | `STRBT_POST_IMM | `STRBT_POST_REG | `STRB_POST_IMM | `STRB_POST_REG | `STRB_PRE_IMM | `STRB_PRE_REG | `STRBi12 | `STRBrs | `STRD | `STRD_POST | `STRD_PRE | `STREX | `STREXB | `STREXD | `STREXH | `STRH | `STRHTr | `STRH_POST | `STRH_PRE | `STRT_POST_REG | `STR_POST_IMM | `STR_POST_REG | `STR_PRE_IMM | `STR_PRE_REG | `STRi12 | `STRrs | `SUBri | `SUBrr | `SUBrsi | `SUBrsr | `SVC | `SWPB | `SXTAB | `SXTAH | `SXTB | `SXTH | `TEQri | `TEQrr | `TEQrsi | `TEQrsr | `TSTri | `TSTrr | `TSTrsi | `TSTrsr | `UBFX | `UMLAL | `UMULL | `UXTAB | `UXTAH | `UXTB | `UXTH ] -> int
val bin_write_insn : Bin_prot.Common.buf -> pos:Bin_prot.Common.pos -> [< `ADCri | `ADCrr | `ADCrsi | `ADCrsr | `ADDri | `ADDrr | `ADDrsi | `ADDrsr | `ANDri | `ANDrr | `ANDrsi | `ANDrsr | `BFC | `BFI | `BICri | `BICrr | `BICrsi | `BICrsr | `BL | `BLX | `BLX_pred | `BLXi | `BL_pred | `BX | `BX_RET | `BX_pred | `Bcc | `CMNri | `CMNzrr | `CMNzrsi | `CMNzrsr | `CMPri | `CMPrr | `CMPrsi | `CMPrsr | `CPS2p | `DMB | `DSB | `EORri | `EORrr | `EORrsi | `EORrsr | `HINT | `LDMDA | `LDMDA_UPD | `LDMDB | `LDMDB_UPD | `LDMIA | `LDMIA_UPD | `LDMIB | `LDMIB_UPD | `LDRBT_POST_IMM | `LDRBT_POST_REG | `LDRB_POST_IMM | `LDRB_POST_REG | `LDRB_PRE_IMM | `LDRB_PRE_REG | `LDRBi12 | `LDRBrs | `LDRD | `LDRD_POST | `LDRD_PRE | `LDREX | `LDREXB | `LDREXD | `LDREXH | `LDRH | `LDRHTr | `LDRH_POST | `LDRH_PRE | `LDRSB | `LDRSBTr | `LDRSB_POST | `LDRSB_PRE | `LDRSH | `LDRSHTi | `LDRSHTr | `LDRSH_POST | `LDRSH_PRE | `LDRT_POST_REG | `LDR_POST_IMM | `LDR_POST_REG | `LDR_PRE_IMM | `LDR_PRE_REG | `LDRi12 | `LDRrs | `MLA | `MLS | `MOVPCLR | `MOVTi16 | `MOVi | `MOVi16 | `MOVr | `MOVsi | `MOVsr | `MRS | `MSR | `MUL | `MVNi | `MVNr | `MVNsi | `MVNsr | `ORRri | `ORRrr | `ORRrsi | `ORRrsr | `PKHTB | `PLDi12 | `RBIT | `REV | `REV16 | `RSBri | `RSBrr | `RSBrsi | `RSBrsr | `RSCri | `RSCrr | `RSCrsi | `RSCrsr | `SBCri | `SBCrr | `SBCrsi | `SBCrsr | `SBFX | `SMLABB | `SMLAD | `SMLAL | `SMLALBT | `SMLAWB | `SMUAD | `SMULBB | `SMULL | `SMULTB | `STMDA | `STMDA_UPD | `STMDB | `STMDB_UPD | `STMIA | `STMIA_UPD | `STMIB | `STMIB_UPD | `STRBT_POST_IMM | `STRBT_POST_REG | `STRB_POST_IMM | `STRB_POST_REG | `STRB_PRE_IMM | `STRB_PRE_REG | `STRBi12 | `STRBrs | `STRD | `STRD_POST | `STRD_PRE | `STREX | `STREXB | `STREXD | `STREXH | `STRH | `STRHTr | `STRH_POST | `STRH_PRE | `STRT_POST_REG | `STR_POST_IMM | `STR_POST_REG | `STR_PRE_IMM | `STR_PRE_REG | `STRi12 | `STRrs | `SUBri | `SUBrr | `SUBrsi | `SUBrsr | `SVC | `SWPB | `SXTAB | `SXTAH | `SXTB | `SXTH | `TEQri | `TEQrr | `TEQrsi | `TEQrsr | `TSTri | `TSTrr | `TSTrsi | `TSTrsr | `UBFX | `UMLAL | `UMULL | `UXTAB | `UXTAH | `UXTB | `UXTH ] -> Bin_prot.Common.pos
val bin_writer_insn : [< `ADCri | `ADCrr | `ADCrsi | `ADCrsr | `ADDri | `ADDrr | `ADDrsi | `ADDrsr | `ANDri | `ANDrr | `ANDrsi | `ANDrsr | `BFC | `BFI | `BICri | `BICrr | `BICrsi | `BICrsr | `BL | `BLX | `BLX_pred | `BLXi | `BL_pred | `BX | `BX_RET | `BX_pred | `Bcc | `CMNri | `CMNzrr | `CMNzrsi | `CMNzrsr | `CMPri | `CMPrr | `CMPrsi | `CMPrsr | `CPS2p | `DMB | `DSB | `EORri | `EORrr | `EORrsi | `EORrsr | `HINT | `LDMDA | `LDMDA_UPD | `LDMDB | `LDMDB_UPD | `LDMIA | `LDMIA_UPD | `LDMIB | `LDMIB_UPD | `LDRBT_POST_IMM | `LDRBT_POST_REG | `LDRB_POST_IMM | `LDRB_POST_REG | `LDRB_PRE_IMM | `LDRB_PRE_REG | `LDRBi12 | `LDRBrs | `LDRD | `LDRD_POST | `LDRD_PRE | `LDREX | `LDREXB | `LDREXD | `LDREXH | `LDRH | `LDRHTr | `LDRH_POST | `LDRH_PRE | `LDRSB | `LDRSBTr | `LDRSB_POST | `LDRSB_PRE | `LDRSH | `LDRSHTi | `LDRSHTr | `LDRSH_POST | `LDRSH_PRE | `LDRT_POST_REG | `LDR_POST_IMM | `LDR_POST_REG | `LDR_PRE_IMM | `LDR_PRE_REG | `LDRi12 | `LDRrs | `MLA | `MLS | `MOVPCLR | `MOVTi16 | `MOVi | `MOVi16 | `MOVr | `MOVsi | `MOVsr | `MRS | `MSR | `MUL | `MVNi | `MVNr | `MVNsi | `MVNsr | `ORRri | `ORRrr | `ORRrsi | `ORRrsr | `PKHTB | `PLDi12 | `RBIT | `REV | `REV16 | `RSBri | `RSBrr | `RSBrsi | `RSBrsr | `RSCri | `RSCrr | `RSCrsi | `RSCrsr | `SBCri | `SBCrr | `SBCrsi | `SBCrsr | `SBFX | `SMLABB | `SMLAD | `SMLAL | `SMLALBT | `SMLAWB | `SMUAD | `SMULBB | `SMULL | `SMULTB | `STMDA | `STMDA_UPD | `STMDB | `STMDB_UPD | `STMIA | `STMIA_UPD | `STMIB | `STMIB_UPD | `STRBT_POST_IMM | `STRBT_POST_REG | `STRB_POST_IMM | `STRB_POST_REG | `STRB_PRE_IMM | `STRB_PRE_REG | `STRBi12 | `STRBrs | `STRD | `STRD_POST | `STRD_PRE | `STREX | `STREXB | `STREXD | `STREXH | `STRH | `STRHTr | `STRH_POST | `STRH_PRE | `STRT_POST_REG | `STR_POST_IMM | `STR_POST_REG | `STR_PRE_IMM | `STR_PRE_REG | `STRi12 | `STRrs | `SUBri | `SUBrr | `SUBrsi | `SUBrsr | `SVC | `SWPB | `SXTAB | `SXTAH | `SXTB | `SXTH | `TEQri | `TEQrr | `TEQrsi | `TEQrsr | `TSTri | `TSTrr | `TSTrsi | `TSTrsr | `UBFX | `UMLAL | `UMULL | `UXTAB | `UXTAH | `UXTB | `UXTH ] Core_kernel.Bin_prot.Type_class.writer
val __bin_read_insn__ : 'a -> pos_ref:'b -> int -> insn
val bin_read_insn : Bin_prot.Common.buf -> pos_ref:Bin_prot.Common.pos_ref -> insn
val bin_reader_insn : insn Core_kernel.Bin_prot.Type_class.reader
val bin_insn : insn Core_kernel.Bin_prot.Type_class.t
val compare_insn : insn -> insn -> int
val __insn_of_sexp__ : Ppx_sexp_conv_lib.Sexp.t -> insn
val insn_of_sexp : Ppx_sexp_conv_lib.Sexp.t -> insn
val sexp_of_insn : insn -> Ppx_sexp_conv_lib.Sexp.t
val all_of_insn : insn list

Memory access operations

type mode_r = Arm_types.mode_r =
  1. | Offset
  2. | PreIndex
  3. | PostIndex

Types for single-register memory access

type sign = Arm_types.sign =
  1. | Signed
  2. | Unsigned
type operation = Arm_types.operation =
  1. | Ld
  2. | St
type size = Arm_types.size =
  1. | B
  2. | H
  3. | W
  4. | D
val compare_size : size -> size -> int
type mode_m = Arm_types.mode_m =
  1. | IA
  2. | IB
  3. | DA
  4. | DB

Types for multiple-register memory access

type update_m = Arm_types.update_m =
  1. | Update
  2. | NoUpdate
type arth = [
  1. | `ADD
  2. | `ADC
  3. | `SBC
  4. | `RSC
  5. | `SUB
  6. | `RSB
]

Types for data movement operations

type move = [
  1. | `AND
  2. | `BIC
  3. | `EOR
  4. | `MOV
  5. | `MVN
  6. | `ORR
]
type data_oper = [
  1. | arth
  2. | move
]
type repair = [
  1. | `POS
  2. | `NEG
]
val compare_repair : repair -> repair -> int
type shift = [
  1. | `ASR
  2. | `LSL
  3. | `LSR
  4. | `ROR
  5. | `RRX
]

shift types

type smul_size = Arm_types.smul_size =
  1. | BB
  2. | BT
  3. | TB
  4. | TT
  5. | D
  6. | DX
  7. | WB
  8. | WT
include module type of struct include Arm_lifter end
val lift : Bap.Std.lifter

lift mem insn lifts instruction.

module CPU = Arm_lifter.CPU
module Insn = Arm_insn
module Cond = Arm_cond
module Reg = Arm_reg
module Op = Arm_op